1. Field of the Invention
The present invention relates to a timing generator of an image input device such as a digital still camera.
2. Description of the Background Art
FIG. 18 is a block diagram illustrating a conventional timing generator that generates four toggles in a cycle in an image input device such as a digital still camera. As shown in FIG. 18, in the conventional timing generator, registers 2a to 2d are connected to multiple comparators 1a to 1d at their respective input terminals on one side, and the count value (H count) of a horizontal synchronizing frequency signal and the count value (V count) of a vertical synchronizing frequency signal are inputted to the input terminals on the other side of the comparators 1a to 1d. The values inputted from a CPU (not shown) are stored in the registers 2a to 2d. When the count value of a horizontal or vertical synchronizing frequency signal (H count or V count) is inputted to the comparators 1a to 1d, this count value is compared with the value of the registers 2a to 2d. If they agree, a comparative signal is outputted. The comparative signals from the comparators 1a to 1d are then inputted to a first OR circuit 3, and the result of the OR operation is inputted, as an enable signal (EN), to a toggle flip-flop 5 through a second OR circuit 4. Here, it is arranged that a load signal (load) for the initial operation instruction from the CPU is also inputted to the second OR circuit 4.
In FIG. 18, reference numeral 6 designates a selector. When an enable signal (EN) of the toggle flip-flop 5 is in high state, signal (D) from the selector 6 is outputted as an output signal Q, at the timing of the rise of a pixel clock. In the selector 6 it is arranged that the value of signal from an inverted output terminal nQ of the toggle flip-flop 5 (hereinafter referred to as “an inverted output value”) and a predetermined initial value are selected, depending on the load signal (load) from the CPU.
Specifically, in the conventional timing generator, at the initial operation, a load signal is provided from the CPU and, in response to this, the selector 6 selects the predetermined initial value. Since an enable signal from the second OR circuit 4 becomes high state by the load signal from the CPU, the toggle flip-flop 5 outputs, as an output signal, the predetermined initial value selected by the selector 6, at the timing of the rise of a pixel clock. At the same time, an inverted output value from the toggle flip-flop 5 is inputted to the selector 6.
When the count value of a horizontal or vertical synchronizing frequency signal (H count or V count) is inputted, the comparators 1a to 1d compare this count value with the value of the registers 2a to 2d, and, if they agree, output a comparative signal. The comparative signals from the comparators 1a to 1d are then inputted to the first OR circuit 3, and the result of the OR operation is inputted, as an enable signal (EN), to the toggle flip-flop 5 through the second OR circuit 4.
When an enable signal is inputted one after another in the above manner, it is arranged such that, at the time of input, the inverted output value of the toggle flip-flop 5 itself is inputted to the toggle flip-flop 5 in a feedback fashion, through the selector 6. This allows to repeat a toggle operation in the toggle flip-flop 5.
With the conventional timing generator described, in principle, the output timing of a pixel data from a CCD (not shown) does not agree with the timing of a processing clock of the CPU. Therefore, if it is desired to rewrite the data of the registers 2a to 2d at a certain timing, the respective comparators 1a to 1d compare the data in a transition state related to rewriting, with the count value of a horizontal or vertical synchronizing frequency signal (H count or V count). If there should be agreement in a moment, a malfunction occurs in the comparators 1a to 1d. This can cause hazard to the timing of the drive pulse of the CCD.
Further, the conventional timing generator requires one register (2a to 2d ) and one comparator (1a to 1d ), per toggle timing. In the practical digital still cameras, however, a complicated special pulse is required in some cases. In order to generate such a complicated special pulse waveform, circuit size is greatly increased.